The Design And UVM Verification Of Ethernet Based Physical Media Additional Layer Interface Chip

With the development of semiconductor technology,chips are receiving more and more attention,especially in the case that domestic chip development is not mature enough.Nowadays,it has entered the era of network society,and the network plays a particularly important role in life.People's lives are almost inseparable from the Internet.Ethernet has been developed since the 1970 s.After more than 40 years of development,the rate has gradually evolved from the initial 10 M to 10 G.The technology is also maturing and forming a unified standard,which is undoubtedly an important component of the network.one.Based on the 12 nm CMOS process,this thesis designs a low-power,low-cost interface chip with Ethernet interface to transmit and receive data.It can support serdes with the highest bandwidth of 25 GE and has 4 channels for transmitting and receiving data.Because the design and verification process of the chip is complicated,the workload is not to be underestimated.Therefore,there is a division of labor in the design and verification process.This thesis focuses on the design and verification process of the PMA module of the chip.Firstly,according to the functional requirements of the chip,the functions of the PMA module are introduced.Then,according to the function of the PMA module,a two-level bit width conversion design scheme is adopted,which is beneficial to save resources and cost,and illustrates the design scheme.The reason.The design scheme is divided into three modules: TXPMA(send),RXPMA(receive),and CPU interface.The TXPMA module contains each small module.The main functions are different data bit width conversion in various modes,and asynchronous FIFO for cross-clock domain.Operation,according to the configuration of the out put data high and low bit reversal,5 times copy,MII interface protocol output;RXPMA module completes the function similar to TXPMA,but is an opposite process,the main function is the bit width in various modes Conversion,cross-clock domain operation,inversion of input data according to configuration,TDM scheduling of 4 digital channels,etc.;asynchronous CPU interface supports Intel CPU interface protocol to read and write the PMA internal registers.In the design function verification,the high-level hardware language System Verilog was used to build the UVM platform for verification.The advanced UVM method was used to build the platform,how to verify the design points,etc.,and finally verified on the VCS tool to confirm the waveform and print.The log flag is correct,the current regression is passed,and the coverage of functions and code is ideal,which proves that the PMA design function meets the requirements.