Design Validation And Testing Of The Interface Chip. Sata2.0 Fpga-based Encryption And Decryption

Serial Advanced Technology Attachmen(tSATA)interface, which transports data from computer to mass storage system or inverse by serial mode, is a new developing interface connecting host to storage system in a few years. Comparing with the traditional IDE interface, SATA interface has some new features: embedded clock signal without extra clock signal line, quite strong recorrect ability from error, power voltage falls to 250mV, support hot-plug, only 4 lines for transporting data by serial mode, and so on. SATA2.0 is the second protocol of SATA interface technology, it makes the external transport speed of storage system from the first one's 1.5Gbps to 3Gbps. At present the SATA interface widely uses in computer domain, but there isn't SATA chips which is independently created.The computer's data often store in the storage system, so it is more important to protect the data in the storage system than to protect the computer. Considered the problem, in the former solve scheme often adopt the way of software encrypt to carry out. But the speed of the software encrypt is slower, the performance of the system is lower and the security of the encrypt software is not very good. Therefore the research on the data encrypt system based on hardware have large meaning. In order to protect the data in the hard disk can't be theft, and solve the problem which the software encryption can't deal with the number of data, this design combines the SATA interface with encrypt function, put the encrypt chip between the host and hard disk which be provided with SATA2.0 interface. The SATA encrypt and decrypt interface system deal with the data come from host and device then transmit to according interface, complete the high speed hardware encryption and decryption.This article analyzes the SATA2.0 protocol, divides the design into physical layer, link layer and transport layer. We complete the design of PHY Packet (PPK), PHY Interface Unit (PIU), Receive Estimate (RE), Send Interface Engine (SIE), Data Process Module (DPM), Send Control Module (SCM), Encrypt and Decrypt module (ENCP) and so on. This design uses the Gigabit Transport processor (GTP) as the high speed transporting PHY, and do the other up layer logic design on Virtex5 FPGA. The articles do a very particular introduction on whole chip design process, and emphasize the verification process of the interface chip, then do the module and system verification on the Modelsim. As the verification and test platform of the chip's function and index, the design base on the ML505 evaluation platform with the Xilinx Virtex5 LX50T FPGA as its core. Use the platform we test the SATA2.0 encrypt chip, the test result indicates the host and device can communicate normally, and the performance can achieve the request of the design.This article contributes to SATA interface and storage system encrypt chip, and have some engineering reference meaning.