Design And Verification Of AES Encrypt-And-Decrypt Module For Bluetooth 4.0

With the development of wireless communication technology, as well as wide use of wearable equipment, people’s normal life could not go on without low power wireless communications. Bluetooth 4.0 LE is a kind of low power wireless communications. Wireless communications require reliable security, in Bluetooth 4.0 LE mode security is guaranteed by AES (Advanced Encryption Standard), and its mode is CCM. Bluetooth devices are often powered by button batteries, so chip designers should consider more about their cost and power consumption. Cost of a chip mostly depends on its area, and power consumption also relates to the area.Bluetooth 4.0 system needs to perform as low cost, low power consumption, and its data transfer rate is not very high. Consider of these characteristics, this thesis designs an efficient hardware encrypt-and-decrypt module with small area. This thesis uses combinational logic structure instead of LUT structure to implement S-Box, simulates these implementations with EDA tools in Verilog HDL hardware description language, compiles with process library cb13fs120 tsmc max, the result shows the structure of S-Box in this thesis saves 7.3% resources than LUT structure. Part the SubBytes to four stages, so the number of S-Box can be decressed, in this thesis, with using only 5 S-Box the resource cost of AES core accounts for only 36.35% of normal AES core. This thesis replaces parallel structure with serial structure, uses one AES core to complete the whole CCM, saves 40% resources than parallel structure.Verify the module with FPGA, at 8 MHz clock frequency,216 bits of data encryption and authentication complets in 39.625ms in this thesis’s design.The results of this thesis show the feasibility of decressing the area consumption while ensuring demand of data throughput for Bluetooth 4.0 AES-CCM hardware module.