Design Of NAND Flash Controller Based On The SOPC

With the rapid development of the new generation of information technology, including big data, cloud computing, and mobile Internet. The needs of the data storage of entire community is growing rapidly. NAND Flash memory devices are widely used because of their high-speed, low-cost, large-capacity and other characteristics. Various types of on-chip system, including SOPC, integrate NAND Flash Controllers.This thesis describes the development of NAND technology and status of Flash storage market. The structure of NAND Flash memory, the standard interface and access operational characteristics are discussed in detail. The principles and specifications of NAND Flash controller design are clarified. Based on the actual needs of a certain type of independent research SOPC, a type of configurable NAND Flash controller using AMBA AHB bus protocol are proposed, which can read and write a variety of asynchronous NAND Flash.The NAND Flash controller introduced in this thesis use configuration and status registers to be controlled, on-chip RAM for data temporarily storage, and multi-level state machines in NAND Flash interface. Meanwhile, in order to solve the data error caused by the external interference or bit flip error, the NAND Flash controller contains an ECC(Error Checking and Correcting) module based on BCH code. This thesis analyzes the encoding and decoding algorithms of BCH code, and gives the corresponding 8-bit parallel circuits. By adding the ECC module, the reliability of data access is dramatically improved only with a very small loss of efficiency of reading and writing. The entire controller has outstanding configurability, scalability, low circuit complexity, and low hardware usage.The verification of the NAND Flash controller includes functional simulation, FPGA verification and testing on SOPC. In the functional simulation stage, a simulation software on computer is used to validation and debugging. Then a FPGA development board with NAND Flash chips is used for actual functional test, in which the results show that the controller described herein can read and write the NAND Flash correctly. Finally, after the certain SOPC is carried out, NAND Flash controller is deployed in practical work. The test results show that the NAND Flash controller is fully able to work properly on this type of SOPC.The proposed and validated NAND Flash controller has been mounted in a certain type of independent research SOPC and used in practical applications. The design ideas and verification methods of the NAND Flash controller are universal, and can be extended to a variety of FPGA or SOPC application environment. The ideas and methods have some practical value.