Study On High Electric Field Reliability Of 90nm CMOS Device

As integrated circuit (IC) process approaches 90nm node, the device reliability problems will be a serious obstacle to the integrated circuit manufacturing development along the Moore's Law. It is found that most of the reliability problems in the devices, whatever nMOSFETs or pMOSFETs, are enhanced in the 90nm process. In addition to the augment in the electric field which can exacerbate device reliability, the changes in the process yet result in some new reliability issues. In the dissertation, the high electric field reliability problems in the ultra-short channel device with ultra-thin gate oxide of 90nm process and how these problems influence the lifetime and parameter degradation of the device has been investigated and analyzed deeply.The dissertation begins with the investigation of the degradation and failure of ultra-thin gate devices under the electric stress. The reliability problems on the oxide become more complex when the oxide thickness approaches 1.4nm. This can be seen from that the expected lifetime extracted using the previous TDDB model is overestimated. But the soft breakdown also makes the device degenerate. The reason is that the increase in the gate current resulted from the tunneling makes the carrier energy difficult to congregate at the local site in the oxide and consequently the thermal breakdown hardly occurs in the ultra-thin gate oxide. Thereby the lifetime of device whose gate oxide thickness is below 1.4nm should not be evaluated by the previous TDDB method.The hot-carrier-effect (HCE) in NMOS device is not improved in the 90nm technology. On the contrary, the degradation due to HCE becomes serious because the lateral and vertical electric fields are increased. It is found that the worst HCE condition in the 90nm devices has moved from the Vg=Vd/2 which holds in the long-channel device to the Vg=Vd. The degradation arose by HCE is ascribed to the lucky carriers generated in the depletion region, the damage at the interface of the source/drain to the gate overlap region and the soft-breakdown in the oxide. By studying HCE of the different structures under various temperature conditions, it is found that the HCE influences the drain current in linear region seriously, and furthermore HCE is weakened with increasing temperature. The HCE can be weakened or enhanced, depending on the conditions of the dynamic stresses. But the final value of the degradation goes to the value of degradation under the direct current stress.The negative bias temperature instability (NBTI) will be aggravated after the 90nm technology node. NBTI causes larger degradation than HCE in PMOS device. So the reliability research on PMOS devices focuses on the NBTI and its helps to look for the improved process to eliminate NBTI in PMOS device. Experiments show that NBTI is enhanced with the channel shrunk. This enhancement mainly takes place in the initial phase of electrical stress. On the contrary to the HCE in the NMOS device, NBTI in the PMOS device will be enhanced when temperature is increased and the degradation varies exponentially with the temperature. Because the Si-dangling bond is passivated under dynamic stress conditions, the PMOS device's degradation is smaller than that under the direct current stress.The damage due to the Plasma still exists in the 90nm technology, which leads to the enhancement in the HCE and NBTI in device. To improve the reliability, improvements of the process and new structure devices are both adopted. The groove-gate device can improve the reliability, especially restrain the drain induced barrier lowing (DIBL).