Uhf Rfid Reader Receiver Carrier To Eliminate The Rf Front-end Research And Design

Based on EPC Global Class-1 Gen-2 protocol, this thesis investigates the receivers of UHF RFID readers and proposes a system architecture of the carrier-leakage cancellation RF front-end. The entire RF front-end and detection link is designed and implemented in SMIC 0.18um RF 1P6M standard CMOS process.According to the analysis of the signal characteristics for return link and the channel of UHF RFID systems, the system specification for receiver is calculated. The carrier-leakage special to UHF RFID readers is analyzed in quantity and the system architecture for receiver is proposed. Then the carrier-leakage RF front-end system is presented and system analysis and calculation are done to settle the module specifications.In the design of carrier-leakage cancellation LNA (Low Noise Amplifier), the design challenges are analyzed and the solutions proposed. Some design rules for RF layout design are summarized. Besides, the design, simulation, modeling and fitting of differential inductor with centre tap are also discussed here.The performance of Gilbert mixers are analyzed in detail, with a concluded guideline for the design of active mixers. The performance of quadrature mixers with shared gm stage is analyzed, and the MGTR (Multiple Gated Transistor) configuration which improves the mixer's linearity and the parasitic vertical NPN Bipolar transistors which reduce the mixer's flicker noise are discussed. The testing setup and results analysis are then given in detail.The carrier-leakage cancellation detection link is also designed. The principle of sub-threshold MOS peak detector is stated and the circuit is implemented. The low offset comparator with auto-zeroing is designed in cascaded configuration of preamplifier and latch to gain high speed. Non-overlapping clock generator is also discussed and designed.Finally, the proposed RF front-end is simulated with 5dBm carrier leakage. The results show a DSB NF of 11dB, an IIP3 of 5.3dBm and an IIP2 of 40dBm, which demonstrates a sensitivity of -80dBm and good anti-interference capacity. The results exceed the system specification and indicate its effectivity in solving the carrier-leakage problem and implementing high performance single chip readers.