Design On Radio Frequency Frout-end Of UHF RFID Reader Chip

UHF (Ultra High Frequency) RFID(Radio Frequency Identification) technology,due to themoderate communication distance and fast data transmission rate,has been widespreadconcerned,Especially for passive RFID tags,which were widely used for retail, food security,health care, logistics, libraries, road charges, intelligent transportation, manufacturing, anddefense aviation and other fields. In addition to, RFID is also an important part of the Internet ofThings. However, the signal which was received and transmited by RFID tags, depend on RFIDreader. So high performance readers are demanded to guarantee the system functionality invarious environments.In order to achieve high performance, most of the RFID readers arecomposed of discrete components, which increase the cost and volume of the reader. Thus, thechip of the reader can be reduced to the volume of the reader, to reduce the cost of the reader.This paper base on ISO-18000-6C protocol and CMOS process is used to design a900MHzRFID reader RF front-end chip. UHF RFID system architecture and the various circuits of RFIDreader RF front-end are deeply researched. In the system design Phase，the main contributionsand result is as follows:1LNA was designed into a2stage structure that leak signal and noise from the circulatewill be eliminated by the first stage of the pre-amplifier, the second stage LNA is the mainamplification to amplify signal. The simulation results show that the system noise is reducedsignal leaked from transimitter is suppressed and the desired signal gain is increased effectively2Single-balanced passive mixer structure was used for the circuit of mixer, the simulationresults show that the single-balanced passive mixer structure can improve the circuit’s inputcompression point and effectively control the noise figure of the receiver. Transmitter power amplifier circuit was designed to a two stage structure. The first stage ispre-amplifier and the second stage is main amplifier. The first stage of the cascade differentialamplifier structure which reduce the requirements of the transistor breakdown voltage, increasethe voltage swing of the power amplifier output, improve efficiency, and also reduce the area ofthe transistor.