Uhf Rfid Reader Chip Key Technologies And Implementation

Due to the moderate communication distance, data rate and antenna size, the ultra high frequency (UHF) band radio frequency identification (RFID) system is getting more attention in recent years in both industry and adaceme. Particularly, the passive tag benefiting from small size and less expensive is widly applicable in logistics, storage, asset management, tracking and tracing, anti-counterfeit, etc. But the power and cost limitation on passive tags requires high performance readers to guarantee the system functionality in various enviroments. So most of the commercial RFID readers now are based on high performance but also expensive discrete components (especially RF modules), that makes readers cost high and hinders the mass adoption of RFID system. The reader chip which integrates the main modules of reader (transceiver, base band processor) into a SOC chip can reduce the cost, power consumption and volume of reader greatly, makes the single chip architecture attractive, especially for low cost low power reader design.This thesis designed the reader chip for 900MHz band passive tag RFID system and implemented the chip on CMOS technology. System analysis, system modeling, architecture design, circuit design, implementation, testing and prototyping are included. In the system design phase, the main contributions and results are:1. By analytical analysis, the closed form solution of unequal symbol length PIE coding power spectrum density (PSD) is derived. The conclusion is consistent with simulation results, and is deducible in the system design;2. By a detailed analysis to the DSB-ASK, SSB-ASK, PR-ASK modulated signal, and FMO/Miller coded returning signal, the power distribution of transmitted signal after the baseband pulse shaping filtering, and the spectrum characteristics of backscattered signal is given. Accordingly, the recommended channel bandwidth and data rate is given and submitted to the state radio regulatory committee (SRRC) as the reference of UHF RFID regulation in China. The reference was accepted in Oct. 2006, and the draft of regulation was announced in May. 2007.The high power local carrier leakage is the most difficult part to be deal with in the circuit design. To process a signal at the level of -70dBm to -40dBm, coexisted with a OdBm local carrier leakage in a 1.8V CMOS receiver, the following new schemes are used:3. A single balanced passive mixer is used as the first stage of receiver, for its high input compression point and low flicker noise, where the latter is important at the absence of low noise amplifier (LNA). Besides, the single balanced structure can provide single-ended to differential conversion, so the off-chip balun can be eliminated;4. The high output impedance of passive mixer will reduce the performance of the conversional DC cancellation structure based on shunt-shunt feedback and full differential amplifier. Instead, buffer stage with high input impedance is needed following the passive mixer. In this design, a 2 stage structure with proper distribution of gain and noise, realizes the mixer buffering, DC cancelling and baseband low noise amplification. And pseudo differential structure based on rail-to-rail amplifier is adopted to accommodate the large DC component sourced from the down-converted carrier leakage.This chip is implemented using SMIC 0.18um mixed signal CMOS technology, the core voltage is 1.8V, digital I/O voltage is 3.3V, occupies 3.2~*3.5mm~2, current consumption is 140mA (on chip driver amplifier is not included). Testing results show that the baseband output noise is -70dBm/Hz at the presence of OdBm carrier leakage. The output noise is dominated by the down converted phase noise of carrier leakage. This result gives an instructive conclusion:5. In the direct conversion RFID receiver, the phase noise will be partially cancelled during the down conversion, due to the correlation between the phase noise of carrier leakage and local oscillator for down conversion. In this design, the measured cancellation is about 17dB, which helps the more detailed phase noise requirement of the frequency synthesizer.To verify the chip functionality, a reader prototype is designed which includes reader chip, digital receiver, protocol processor, interfaces, power management and other parts. Testing shows that the prototype can realize complete reader-tag communication. The PC controlled upper machine send the command to reader, process the returned and decoded data, and display the verified EPC code. The longest communication distance is 30cm, when transmitting 20dBm power. Experiments show that beyond the output power, the phase noise of carrier leakage dominates the receiver noise, so increase the output power does not help. To reduce the influence of carrier noise to the receiver is the main task of the future work.