The Key Technology Research And Design Of Single-chip UHF RFID Reader

Due to larger storage capacity, higher data throughput, rewritable ability and non-line-of-sight transmission, RFID has received great attentions in both industry and academy. Because of the limitation on the power dissipation and cost of passive tag, the reader is required to have high performance to guarantee the system functionality. Recently, most of the commercial RFID reader systems are based on high performance discrete components which results of the high cost of the reader and hampers the development of commercial RFID systems. The solution to integrate the transceiver and digital baseband processor in a chip can reduce the power dissipation, volume and cost of the reader greatly, which draws attention to the field of RFID technology.This thesis investigates the important technologies to implement a UHF RFID reader chip operating in 900MHz frequency band and designs the main circuit modules which are fabricated on CMOS process. The whole design procedure includes protocol analysis, system structure investigation, system specification calculation, circuit design, implementation and testing. And the main contributions and results are:1. The RFID protocol is analyzed and development situation is studied. On the basis of that, the structure of the reader receiver is definite. Furthermore, the thesis calculates the system specification such as sensitivity, phase noise and input third intercept point and so on.2. A bandwidth tunable channel-select filter used in baseband is designed. According to the reflected signal data rates ranging from 40kbps to 640kbps in the protocol, the bandwidth can vary from 100kHz to 1.3MHz. A fourth order Chebyshev filter is chosen and the circuit is Tow-Thomas structure. A parallel capacitive array is used, which makes the reader baseband processor to control the filter bandwidth by varying the capacitance. Due to the maximum bandwidth of 1.3MHz, the opam in the filter with a unity gain bandwidth of 60MHz and gain of 62dB is designed. The filter is implemented on UMC 0.18μm RF CMOS technology. The measurement results show that the cutoff frequencies are 804kHz and 602kHz respectively when the bandwidths of filter are tuned to be 800kHz and 600kHz. However, there is offset existing between the measure results and simulation results, when the bandwidths of filter are tuned to be 1MHz and 1.3MHz.3. An automatic gain control circuit is designed on the basis of the system specification. The VGA is composed of a Gilbert cell amplifier and a gain controller which improve the VGA's gain variation linearity in decibels. The current mirror peak detector is designed whose output is sent to the error amplifier. The AGC is implemented on UMC 0.18μm RF CMOS technology. The post layout simulation results show that the the gain tuning range is from 20dB to 40dB. And the linearity and noise figure can satisfy the operation requirement.4. To fulfill the specification requirement, it is necessary to design low phase noise, wide tuning range and fast settling time of the frequency synthesizer. A delta-sigma modulator is used to tune the Phase Locked Loop fractional division modulus and optimize the PLL phase noise performance simultaneously. As a result of that, a 4th order PLL is designed which is the difficulty of this thesis. In order to confirm the wide VCO tuning range and meet the phase noise requirement, a digital switched capacitor array is chosen. Finally, a high performance charge pump is applied to reduce the current mismatch. The whole circuit is implemented on UMC 0.18μm RF CMOS technology. The post layout simulation results indicate that the settling time is 100us and phase noise is -123dbc/Hz@500kHz. Measurement results and simulation results indicates that the circuits can satisfy the UHF RFID reader chip application requirement. And some measured specifications are perfect, which lays a solid foundation for future work.