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Device Based On Cmos-compatible Process Model And Parameter Extraction

Posted on:2009-11-17Degree:MasterType:Thesis
Country:ChinaCandidate:X ZhuFull Text:PDF
GTID:2208360245461027Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The emerging of Smart Power Integrated Circuit (SPIC) is important to increase the system's reliability, reduce the cost, weight and volume, and also make the system smart and miniaturized. SPIC is widely used in many fields such as telecommunication, computers, automotive and household appliances. It has enormously pushed the further development of the electronic industry and is called as "the second electronic technology revolution". SPIC, which integrates the high voltage devices and the low voltage circuits together, should be carefully considered with the isolation technology. If the BCD technology is used, then it's expensive and the process needs high precision. According to the patent technology of Optimized Variational Lateral Doping made by Prof. Xingbi Chen, it is possible to make SPIC with CMOS-compatible technology instead of BCD. In this way, it will greatly reduce the cost, make the design of the external circuits easier and in the same time improve the system's performances. Based on the CMOS compatible technology, this paper has a research on SPIC in the point of device model and model parameter extraction.In this paper, at first the basic model theory is introduced, then the development of models including MOSFET and BJT is reviewed. After the used CMOS-compatible technology being described, the process of extracting the MOSFET LEVEL = 3 model and extracting Gummel-Poon model of bipolar transistor, including the data obtaining, the device structure analysis and the optimized choice of extraction strategy is discussed in detail, assisted with the soft MEDICI and AURORA. The obtained models and model parameters are used in the circuits design and simulation through the tools of circuits simulator Spectre. The analysis of the method and the results of the testing are also discussed in the paper. It emphases on the testing analysis of MOSFET and the pnp transistor, also containing extracting the minority-carrier lifetime through MOS structure. And finally examples are taken to analyze the cause of the circuits' failure.
Keywords/Search Tags:SPIC, CMOS-compatible technology, model, parameter extraction
PDF Full Text Request
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