High-speed Parallel Signal Processing Board Data Interfaces And Control Of The Fpga Design

With the development of the current society, the more and more real-time information need to be processed in time. So the high performance CPUs and boards are required. To satisfy these kinds of demands, various boards appear. They not only process information rapidly and efficiently but also keep developing and consummating. These data-processing board need to communicate with many kinds of interface and need to exchange data each other between devices on the board. This dissertation designed the interfaces to DDR,DSP and PC and designed the inner data-lane of FPGA.Firstly, the background of the general signal processing board is introduced, including processing-chips, devices on board and introduced the general situation of the development of the processing-board and several kinds of bus. And at the same time, my main job is present as well.Secondly, the PCI specification is introduced and put forward the timing between the board and the PCI. Bus ; The basis performance of the DDR SDRAM , electronic specification and the function register are introduced also, at the same time , the dissertation designed the timing of interface between FPGA and DDR SDRAM ; the dissertation describe the DSP—TS202's general situation and provide the designation of the timing between DSP and FPGA.Thirdly, the flow of develop Altera Inc's product is present in the dissertation and realize the timing-designation among different model and the control-core of the DDR is expatiated particularly.Fourthly, the dissertation introduce the architecture of WDM driver and the way to develop driver.At last, the whole system is proved to be running exactly and normally through writing increment data from PC to DSP. In a word, this dissertation realized communication of the inner data lanes and specification of external interface; at the end of dissertation, the ways to develop and perfect the whole designation are listed.The main job in this dissertation is:1. Realize every interface's timing and the processing board can receive or accept data accurately.2. Finish the data lane designation and the data can be transfer data from PCI bus to DSPs accurately to process.3. Finish the program of DDR's control-core using VHDL.4. Finish the PCI driver.