Architecture And Implementation Of The High-effective Viterbi Decoder

In modern communication, Error-Correcting Codes are often used to improve the system performance, among which the convolutional code is adopted widely because of its excellent capability. The Viterbi algorithm is a maximum likelihood decoding procedure for the convolutional code in essence. In practice, how to realize the Viterbi decoder effectively is important to satisfy the actual demand, so several methods that meet the demands are discussed in this paper. In order to increase the decoding speed of the input encoded data, the pipelining and block processing methods are employed in the ACS unit that is the bottleneck of the Viterbi algorithm, so that the operation of the feedback loop could be completed in several clock cycles. Subsequently, some details about how to decrease the scale of the circuit of the decoder are introduced. The tradeoff between speed and resource is described when an area-efficient ACS architecture is used. Finally, with the modern EDA technology, a high-speed Viterbi decoder is realized based on the radix-4 trellis instead of the traditional radix-2 trellis. In the course, some new problems appeared in the algorithm with radix-4 trellis are analyzed in depth. The algorithm is optimized to make the circuit easier to be realized using FPGA device, and the decoding speed is increased because of the multilevel pipelinings.