Usb 2.0 Device Interface Ip Core Design

Because of a number of merits of Universal Serial Bus, such as cheap price, easy use, simple protocol, standard interface and easily expanding of ports, it is widly used in computer interface area. So it will be necessary to integrate the USB function in different SoC systems. This paper designes and implementes the USB interface IP core. The designer need to combine the ability of ASIC system design and the ability of protocol comprehension, so this paper has both theory and practical value.With the fast progress of IP cores, the study focus will turn to how to improve the reuse of IP cores, connect the IP cores effectively and build the SoC chip quickly. At first this thesis reviews the technique of IP core reuse. In this part, three different IP cores and their develop flow followed by three usual bus on chip are discussed; Then the paper describes and analyzes USB2.0 protocol from the system configuration, formats of packet, ways of transfer and transform of six states of device.The high-level design synthesis flow is depicted as follows. Using a lot of successful designs of USB interface chip as references, the USB2.0 is partitioned to six function modules which are UTMI, protocol controller, buffer interface and arbitration, state register, buffer and wishbone interface. These modules use FSM to model and use Verilog HDL to complete USB2.0 IP core.In the design, the main functions of UTMI module are to supply the data transfer channel between transceiver chip and module of protocol controller, check the events on USB bus and complete the transformation of device in variable state. Module of protocol controller is the most complicated module in all USB2.0 device interfaces. It is charge of resolving and sending the data that has received, also includes erasing or adding PIC, CRC verification field. Module of state register is used to store the informations in each port and operation state of USB device. Module of buffer interface and arbitration depend current situation to decide to send data in buffer to interface circuit or controller linked with Wishbone, meanwhile store these data temporarily.At last, the author simulates and synthesizes the USB2.0 IP core. Function simulation has been completed on each module and high-level by using VCS. At the synthesis stage, we use Design Compiler to logicly synthesize the IP core. Depending on the characterers of USB IP core, we apply appropriate strategy of synthesis and method of optimization. Finally, the results are analysed.