USB2.0Device Controller IP Core Design And Verification

Universal Serial Bus (USB) is an interconnection standard widely used in computers and peripheral equipment. Compared with traditional parallel interface, it has simple connection, scalability and other important advantages. In this thesis, we designed a USB2.0device controller IP core. This IP core can be embedded into the SoC chip as an function module, which make the SoC chip could communicate with the PC.Based on USB2.0protocol specification, we proposed a new system architecture of a USB2.0Device Controller IP core. This architecture’s module division is based on the goal that the function of each module is independent and its signal flow is clear. This IP has two part of interface. one that is connect to the physical transceiver and base on the UTMI protocol, while the other one is connect to application and designed to meet most applicational condition and has great flexibility as well. So it can be easily redesigned according to specific application. We design four modules on the basis of the architecture:the operating mode control, packet processing, transaction processing, and control of the transmission. The operating mode regulate the module to complete the reset detecting, high-speed handshake, suspend and suspend wake. Transaction processing module complete the three steps (token, data, handshake) of an USB transaction. Packet processing module is responsible for detecting PID(pocket identifier) and checking the CRC at the time of receiving a packet, While sending a packet, it requires assemble the packet and add CRC. Control transfer module is designed for USB device enumeration, it uses hardware circuit to replace the function of the MCU and USB firmware. The IP core is perfect in function, it support both high-speed (480Mbps) and full speed (12Mbps) transmission modes.This thesis presents the plan and simulation of each module, and we made a function simulation of each module by the use of modelsim tool. Then we make a functional verification for the IP core in transmission level, transaction level and packet level.The results show that the core we designed can meet the requirement of the USB protocol specification. Finally, we design a FPGA test board, then we complete physical verification of the IP core by using the Xilinx design tools and the USB protocol analyzer. Testing results show that the IP core operating well, and it can realize the enumeration process smoothly.The designed IP core can be used as a generic USB2.0device controller to developing a USB device. We can also use the IP core as a function module that embedded into the SoC to realize complex function. The interface between IP core and the application layer can be modified according to the actual need. This IP core is universal and very practical.