Logic Design And Implementation Of USB2.0PHY IP Verification System

As a new generation of standard bus interfaces, Universal Serial Bus (USB) not only can simultaneously connect up to 127 devices, but also has plug and play,fast and so on, so that the connection between the host and devices is more efficiency and convenience. Because of the many advantages of USB bus, research on the USB interface with faster transmission speed and more reliable performance is one of today's trends. Therefore, whether from the market demand, or to enhance China's chip design capabilities, the development of USB2.0 interface chip is very urgent requirement. In the current SoC design, the verification of the whole design work accounted for about 70%. In order to improve the verification system and reduce chip development time, verification can not be ignored key in the IC future.According to the project requirements of USB2.0PHY IP , this paper researches the overall design program of USB2.0PHY IP verification system as well as high-speed data transfer logic design implementation. The paper has taken top-down modular logic design, to determine the division of the every functional modules. In a full understanding of the USB2.0 protocol and UTMI specification, based on the verification system for the every chip hardware platform and work of the working principle of timing in-depth analysis to determine the verification system in high-speed mode, the paper programmed each functional RTL-level module by using hardware description languages, completed the simulation and synthesis by ISE Simulator, ultimately successfully used for USB2.0PHY IP hard-core, high-speed functionality and reliability verification.