Usb Controller Ip Design

Universal Serial Bus ,a new interface between computers and peripheral equipments, is applied to more and more fields. This paper, based on the high level synthetical IP design flow, has accomplished the design of USB controller, the important part which performs the function of USB Specification.This paper analyzes and researches in detail the Universal Serial Bus 2.0 Specification and USB2.0 Transceiver Macrocell Interface Specification. It also discusses detailedly the important parts related to this design. It completes the general design of USB controller and the design of protocal engine controlling module, data buffer module, memory arbiter module, UTMI protocal interface and microcontroller interface module.This paper brings forward the idea of State Machine application aiming at the characteristic of difficult design and also summarizes it. It completes the logic synthesis of the whole system and the detailed accomplishment of software validating and the scheme of FPGA validating. Futhermore, it programmes the testbench and implements the functional simulation and timing simulation after route. Moreover, it reserches the application of all kinds of EDA tools. In the end, it summarises the difficulties and the innovative idea of the project, and gives the development and the improvement of the project in the future.The difficulties of this project are as follows:1. The application of IP flow and applying it to the whole design2. The indigestible concepts of USB protocol such as endpoint, pipeline and so on3. The general scheme of USB controller and the division of functional modules4. The state machine of every module of the controller and how to design the state machine effectively5. The switch of two buffers' points6. The programming of testbenches7. The mixed use of different EDA tools The innovation of this project is as follows:1. The characteristic of two buffers which reduce the delay between microcontroller and device driver software2. Supporting the DMA transfers between endpoints and external memory which needs no interference of CPU3. The internal design of DPLL which resolves the problems of high frequency4. Using EAB module of FPGA's own as the buffers of endpoints in the scheme of design which will reduce the cost of development...