Design And Implementation Of Data Control Module In USB2.0 PHY Layer Without Crystal Oscillator

As a standard high-speed serial bus interface,USB universal serial bus has a very high data transmission speed,which can meet the requirements of many high-speed data transmission applications.Moreover,because of its advantages of simple power supply,flexible connection,good compatibility and hot plug support,it has become one of the standard extension interfaces and necessary interfaces used by all kinds of data transmission systems.USB2.0 bus can support data communication at high speed(480Mb/s),full speed(12Mb/s)and low speed(15Mb/s).High speed is applied to digital cameras,full speed is applied to audio transmission,low speed is applied to asynchronous transmission such as mouse.This paper starts with the requirements of the project,according to USB2.0 protocol,USB bus architecture,data stream type,UTMI interface specification,data transmission mode,for the data control module of USB2.0 PHY layer without crystal oscillator,detailed understanding to determine the function of each module,using top-down design method,Frequency calibration of crystal-free circuit and switching of working mode,send and receive data state machine,data stream buffer processing,NRZI encoding and decoding mechanism of data,bit-stuff,bit-unstuff,serial parallel conversion,filling and removing of SYNC/EOP signal,CDR data clock recovery and data detection,etc the module has done a detailed analysis and design,based on the in-depth understanding of the foundation to make verification.The 16 phase oversampling CDR is composed of five modules: data sampling,buffer synchronization,edge detection,decision and data selection.The received serial data is continuously sampled by 16 phase equispaced multi-phase clock output by PLL module,and stored in two groups of 16 bit registers.The corresponding bits of the data in the two registers are XOR detected,and the relative edge position moves backward for half a cycle.The phase position is the reliable sampling point of the data,and the data sampled by the phase clock at this point is the data Output.It can effectively avoid the problem of serial data clock recovery under the condition of frequency deviation at both ends of transceiver.Features: the tolerance of frequency deviation is larger,the adjustment of phase accuracy is higher,the burr problem of high frequency16 phase clock switching is avoided,and the transmission error rate is improved.The designmethod has the advantages of simple algorithm structure,small time sequence pressure and more process environment requirements.The USB2.0 crystal-free clock calibration circuit design adopts the preprocessing idea to SYNC the synchronous code in the SOF(Start of Frame)package Code pre calibration,which advances the time point of calibration,reduces the frequency deviation to a small range,calculates the value of SYNC signal number single bit pulse meter,retains the rest part of its information,and uses the compensation idea to fully sample the frame start SOF package,which is accurate,fast and efficient.Determine the logic design scheme under each mode,use Verilog-HDL hardware description language to complete the RTL level(register transfer level)design of each module,use Synopsys simulation integrated tool,use mature verification environment for functional simulation verification,and independently design the logic integration and static timing analysis,and finally successfully verify the functional integrity and reliability of the design.