Mstp Chip System-level Design And Fpga Verification

The great challenge in face of Telecommunication Service Providers is to accommodate client's rapidly increasing data traffic, as well as support traditional voice and private line service. Existing SDH/SONET network can not offer an efficient transmission infrastucture for new data services, such as Ethernet & SAN. However the expense on constructing a whole IP network is too expensive to be feasible. Emerging MSTP technology is capable of flexibly and efficiently handling various data traffic on SDH/SONET network, and greatly exploring the potential transmission capacity of existing network. Since presently the kernel circuits inside domestic vendor's MSTP facilities are mostly relied on imported ICs, the research and development of MSTP ASIC is very important for promoting our state's competing capability in telecommunication market.This paper firstly describes fundamentals of MSTP technology, including features of MSTP, definition and functional models of MSTP facility. Secondly a design scheme of MSTP ASIC is presented from a system-level perspective, the function definition and module partition is also finished. Then the key technologies involved in development of MSTP system are described in detail, which include SDH, GFP, Virtual Concatenation and LCAS. Finally the design scheme and implementation method for parallel frame aligner, 8B/10B encoder/decoder, GFP-T encapsulating circuit and virtual concatenation circuit are discussed.The Top-Down design methodology and RTL-level Verilog HDL are adopted through this paper. The functional simulation, staic timing analysis, logic synthesis and dynamic timing simulation are completed by utilizing the collaborative simulation function between ModelSim and QuartusII. The FPGA physical validation is finished on Altera's Cyclone series FPGA device EP1C6T144C8. Using ModelSim instead of QuartusII to perform dynamic timing analysis remarkably improves the efficiency of simulation and increases the test vector's migration capability and commonality.The critical technologies in this paper consist of parallel frame alignment, which relaxes the timing requirement; utility of FPGA device's embedded PLL in high quality clock generator; study of GFP-T mapping mode, an innovative design scheme and practical implementation roadmap is provided; finally the design and validation of virtual concatenation circuit is discussed.