Chip Design And FPGA Implementation Of VCAT And LCAS In EoS

Along with the development of Internet technology and B-ISDN, data packet operation grows faster than ever, becoming the main operation of telecom market. However, the IP network is not able to provide alone the reliability requirement of the public transmission network and it also takes too much cost. As a result, people brought forward a kind of solution that transmits Ethernet operation over SDH, called Ethernet over SDH, EoS for short. The birth of EoS technology makes full use of current network resources and achieves efficient transmission of data operation over SDH network.Usually, EoS technology applies Virtual Concatenation (VCAT) and Link Capacity Adjustment Schemes (LCAS) to settle two problems: One is that VCAT technology provides the Ethernet data transmission a fit SDH channel to settle the data rate mismatch between Ethernet and SDH payload. It also increases the channel granules and bandwidth utilization ratio of SDH network. The other one is that LCAS technology, based on VCAT, can adjust bandwidth resources dynamically according to real time change of the data bandwidth and increase the utilization ratio of SDH network efficiently.According to the researches on VCAT and LCAS, the author introduces a feasible, economic and efficient way to implement the integrated design of VCAT and LCAS in EoS system. Function definition and module partition are taken and the chip design and FPGA implementation of VCAT and LCAS is accomplished.First of all, the paper introduces technology details of SDH, VCAT and LCAS in EoS System. Then, the paper introduces in detail the design of VCAT, LCAS FSM, Clock_enable_control module and POH processing module. And the paper completes the RTL hardware description of each part by synthesizable subset of Verilog HDL. The testbenches are written according to function request and the simulation results are presented in the paper. The paper introduces FPGA implementation flow and completes the design following the flow. Synthesis, floorplan and PAR are implemented in the FPGA developing environment. At last, the paper analyzes the metastability problem and provides one solution to this problem.The Top-Down design methodology and RTL-level Verilog HDL are adopted in this thesis. Based on Xilinx ISE 9.1i integrated environment, functional simulation, logic synthesis, floorplan, PAR and FPGA programming of the design are completed. Use Mentor Graphics Modelsim to perform functional simulation and dynamic simulation with timing, similarly, use Synplicity Synplify Pro 8.1 to perform synthesis. ISE 9.1i provides software interfaces, which can be started in ISE 9.1i. Use Floorplanner and FPGA Editor which are provided by ISE 9.1i to perform floorplan and PAR respectively. Considering the design scale, performance and price of diversified FPGA devices, Xilinx Spartan-3E series FPGA device XC3S500E-4FG320C is chosen for implementation of the whole design. After downloading the created programming file into FPGA E~2PROM, the chip is implemented in Xilinx Spartan-3E Starter Kit board .The main merits of the paper are as follow: a complete design solution is provided and the integrated design of VCAT and LCAS in EoS system is achieved. Several circuit modules, such as SDRAM Controller, asynchronous FIFO, CRC, Clockenable controller are implemented. And the metastability problem is settled properly.