If Digital Receiver Design

Digitalization is a very important trend of modern electronic system. As an important part of digitalization of electronic system, digitalization of receiver is very important for the research on digitized receiver. With the fast development of digitalization theory and microelectronic technology, it is possible to design hign_speed IF digitized receiver.In this paper, a structure of a efficient DDC (Digital Down Converter ) based on costas loop is presented firstly, and then the project to design a IF digitized receiver is proposed, finally, the realization of DDC system on FPGA chip and testing of this receiver system are introduced. The results of computer simulation and testing indicate that the system could work well and the desired requirements could be achieved.The main contents of this paper include: the theory of IF digitization (sampling and quantization, quadrature demodulation, carrier synchronization and digital filtering ), introduction of a structure of efficient DDC, the simulation of the system project, the design and implementation of the DDC part and analysis result.