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Full Digital QPSK Carrier Synchronization Research And FPGA Implementation

Posted on:2017-01-16Degree:MasterType:Thesis
Country:ChinaCandidate:L L YuFull Text:PDF
GTID:2358330485495588Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Software defined radio can modularize its function, it has greater flexibility, better scalability and other advantages, which makes engineers have an in-depth study in contemporary digital communications industry. Its central idea is that it can achieve the relevant function of different algorithms on the common hardware platform through the transformation of the function module algorithm. In relation to the BPSK, QPSK modulation has better spectral characteristics and higher spectrum efficiency, and it has strong anti-jamming performance and faster transmission rates. Therefore, at the transmitter side this paper use QPSK to modulate the baseband signal to be sent, at the receiver side it use FPGA technology to implement algorithms of each module, so that the carrier synchronization system function of the receiver can be achieved.Firstly, this paper described its main technical and partical theoretical knowledge, which has laid a theoretical basis for the next system simulation and plan design. Then this paper discussed several different carrier synchronization methods, and selected Matsuo loop carrier synchronization method to be the appropriate carrier synchronization method for the present system in the end. According to the synchronization mode have selected, this paper designed the entire digital communications system and its main modules, and implemented on the FPGA platform. The system modeling simulations by MATLAB visually verify the correctness of the design. Then this paper used the ISE development software, wrote Verilog HDL code, and made the FPGA implementation for transmitter and receiver designed by system, and simulated and validated the every part through Modelsim and Chip Scope on a common hardware platform.Experimental results show that the loop structure is simpler and does not require multiplication; it is easier to be implemented and occupy less hardware resources. It can be seen that the carrier synchronization loop can convergence quickly, and remain steady through the MATLAB simulation analysis. In a certain frequency offset, the receiver side can recover the original baseband signal emitted by the transmitter side, which achieved the anticipated effect; it has proved the correctness and the realizability of the system scheme design, which has met the actual needs of the system.
Keywords/Search Tags:software defined radio, all-digitized receiver, carrier synchronization loop, FPGA, QPSK
PDF Full Text Request
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