Design And Implementation Of Multi-Mode Digital Communication System Receiver Based On FPGA

After the concept of software radio is proposed, all digital receivers get fast development. According to its thought, it is to put the D/A, A/D closer to the antenna in the design and implementation of the communication system.For the multi-mode system digital receiver system, it combines many kinds of speed, many kinds of modulation and demodulation methods, many kinds of encoding and decoding methods, and arbitrary multiplexing. It achieves a wide range of content. In the laboratory of existing communication laboratory equipment,because of each experimental unit running independently and containing single function,it is unable to complete system level experimental operation. This paper summarizes the shortcomings of the communication experimental equipment and uses the characteristics of high integration and field programmable of FPGA. It has been designed to verify the validity of the system of the multi system digital receiver experiment system.This paper designs and implements an experimental system which is different from the traditional experiment box and is different from the actual communication system. It can provide open and operable software, hardware platform. Students can not only complete the experimental contents of the existing individual modules, but also can carry out the communication between the modules and system level in this experimental system. At the same time it also can make their own design and verification. It is helpful for students to understand their knowledge and develop their practical ability.According to the basic model of the communication system in this paper, the design of the multi system digital receiver is divided into the following parts:intermediate frequency demodulation synchronization module?down conversion module?deinterleaving module?decoding module and demultiplexing module.In addition to the needs of the system,at the same time also designed carrier generator module?system clock frequency dividing module and controller module.In the intermediate frequency demodulation synchronization module,in order to save the internal resources of FPGA,the ASK, FSK,DPSK and QPSK signals are all used in coherent demodulation mode. It uses all digital COSTAS loop carrier extraction technology and GARDNER bit synchronization algorithm for IF demodulation and synchronization.In the decoding module,the principle of the communication in the course of Hamming encoding and parity codes of two basic encoding and decoding are designed and realized.Using the idea of connecting module in time division multiplexing,it can complete any road to 2-32 road signal frame connected.Carrier generator by using DDS technology,waveform of arbitrary shape with high frequency resolution can be generated.In this paper according to the relevant content of the communication engineering courses and related literature,the model of each module in the digital receiver is extracted and the design and implementation of each model in FPGA are carried out.At the same time, because the resources needed for the digital receiver are different, the appropriate FPGA chip is selected and the design of its hardware circuit is given.Finally, the implementation process of each module in FPGA is given, and the system simulation, test and analysis of the digital receiver of this design is done.The test results show, it is able to complete the synchronous demodulation of the received signal, baseband decoding and tap, etc. And functions and indicators are designed to meet the design requirements.