Fpga-based Digital If Receiver

Digitalization is a very important trend of modem electronic system. As an important part of digitalization of electronic system, digitalization of receiver is very important for the research on digitized receiver with the fast development of digitalization theory and microelectronic technology, it is possible to design high-speed IF digitized receiver.This thesis is focused on the study of broadband, high efficient digital IF receiver. The significant works are as follow:1. Some key techniques, such as digital down converter (DDC), digital filter etc, are discussed. FPGA programming for the DDC with CORDIC algorithms and the distributed arithmetic (DA) for digital filtering are accomplished.2. Four kinds of DDC structures are analyzed and their performances are compared. The classical structure of digital IF receiver is reformed, an efficient DDC structure without multiplier is applied.3. The hardware circuit design and manufacture of digital IF receiver is completed. For each software module, VHDL programming, simulation and debugging is accomplished. Distributed algorithm is applied in the design of FIR filter. The OBC coding and parallel/serial structures are used to improve speed and reduce resource consumption in FPGA. The experimental results show that the designed digital IF receiver are correct and effective. Compared with the multi-level decimation structure, the consumption of the multiplier, trigger and many other FPGA resources in this designed DDC structure are reduced significantly.