32 Mips Architecture-based Dual-launch Pipeline Logic Design

Central-processor is the locomotive that drive the development of computer technology and industry. The technology of CPU's design and manufacture is the base of the IT technology and industry. Carry through the work of CPU design possess the momentous academic value and realistic value. Pipeline technology is the kernel technology of modern CPU design. It's the key of the CPU efficiency.RISC is the new CPU design technology that developed in 1980s. Its emergence brings the far-reaching effect to the whole computer domain. The crucial trait of RISC architecture is that it can fit the pipeline compatibly. MIPS is a eximious delegate of RISC. So many traits of MIPS fit the pipeline availability, and it is the excellent architecture of pipeline design.The aim of MIPS pipeline is that one instruction completed in one period averagely. Pipeline increase the CPU efficiency greatly, but the exist of instruction correlation make the pipeline block and delay frequently, as a result it can't achieve the aim that one instruction completed in one period averagely.For increase the CPU efficiency more, base on the research of existing 32-bit MIPS pipeline, this paper create the double-launching pipeline. by this design, one or more than one instruction completed in one period averagely, and increase the CPU efficiency remarkably.The main tasks of this paper are as follows:(1) Carries on the analysis to 32-bit MIPS processor architecture and the MIPS five stages pipeline, and obtains the restriction factor of MIPS pipeline efficiency. And analyzed the feasibility of further enhancing the MIPS pipeline's efficiency.(2) Research the instruction launch strategy, controls correlation processing and data correlation processing of 32-bit MIPS's double-launching pipeline. Obtained the design modes: Static launch, Optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path.(3) Achievement designs by the platform Xilinx ISE 5.2i, uses the Verilog hardware description language to carry on the design description to the double-launching...