Design Of Mips Embedded Microprocessor

Embedded microprocessors are widely used in industrial control, communications, consumer and military fields. In this paper, one 32-bit MIPS microprocessor architecture is studied, then an embedded RISC microprocessor with low power consumption and security features, which is fully compatible with 32-bit MIPS instruction set,is designed. The major work in this paper is as follows.This paper firstly introduces some key technologies of the microprocessor's architecture, such as parallel technologies, cache technologies and low-power optimization technologies. Then it introduces MIPS32^TM architecture, including register organization, instruction set and the compiling process.Then, the overall structure of the design of microprocessor in this paper is presented, followed by the introduction of two parts: the design of microprocessor's core and Cache.Microprocessor's core adopts the technology of six stages pipeline, resolving the timing sequential bottleneck of the traditional five stages pipeline, increasing the processor's frequency dramatically by adding RF level. The resource conflict, data conflict and control conflict, which are offen encountered in pipeline design, get the corresponding solutions.Then, the current security problems, which microprocessors facing now, are analyzed. We modify the Cache structure so that it can effectively resist the side channel attacks with lower power consumption. The main improvement on the cache is that we add Small Cache between the level one cache and the main memory, so the attacker can't obtain the mapping relationship between the cache and main memory, and data security is improved.Finally, the tactics and scheme of the microprocessor verification is proposed. Then, we verify the microprocessor from software simulation to hardware verification to guarantee the correctness of the functionality.To direct at the embedded microprocessors' requirements of high-performance, low power consumption and security, this paper has made useful exploration of the pipeline and cache technology, and has proposed some improvements. The design reaches the desired purpose basically. Synthesized by Synplify Pro 7.7, on Xilinx Spartan-3 XC3S2000 FPGA platform, microprocessor core is able to run at up to 111MHz, the whole system is able to run at up to 53.6 MHz.