| With the rapid development of the integrated circuit industry,the feature size of integrated circuits is constantly shrinking,which has significantly improved the integration and performance of the CPU,and the power consumption has also become lower and lower.With the rise of IoT applications.As the core of the Internet of Things application,the microprocessor makes the demand for the microprocessor in the market increase rapidly,and the application scenarios are constantly expanding.It is applied to all aspects of our lives and constantly changes our way of life.The start of the trade war made us realize that my country’s key technologies such as micro-processing design and chip technology lag behind the international advanced level.This problem can be solved fundamentally through independent research and development of a microprocessor.This thesis is based on an in-depth analysis of the data path and instruction system architecture of the RSIC processor.Completed the design and simulation verification of a microprocessor compatible with the MIPS32 instruction set architecture.The main research contents and results of the thesis are as follows:(1)Based on the comparative analysis of the computer system architecture,the MIPS instruction architecture is deeply studied,including the types of registers in the open source MIPS processor,instructions and instruction formats,addressing methods,etc.Based on the design requirements of the task,the overall structure design of a 32-bit RISC microprocessor with a system frequency of 50 MHz,standard unit door number20 K and a power consumption of 10 m W was completed.(2)Compare and analyze the pipeline architecture,based on the 5-stage pipeline structure,give the overall framework of the thesis design and the design scheme of the5-stage pipeline.Through in-depth analysis of the correlation issues generated by the execution of instructions in the pipeline.The solution methods and processing models related to pipeline data,control and structure are obtained,and the model design of precise abnormality is obtained,and the specific process of abnormal processing in the system is optimized.(3)The Verilog hardware description language is used to complete the design and implementation of the functional units in each stage of the pipeline,including: PC module,ROM register and IF＿ID module in the fetch phase,ID module,Regfile module and ID＿EX module in the decoding stage,EX module and EX＿MEM module in the execution phase,EX module and EX＿MEM module in the execution phase,The MEM＿WB module and four special registers in the write-back phase,the peripheral bus WB module,And carry on the simulation verification of each stage module,accord with the design requirement.(4)Based on Modelsim software to build a verification verification environment to verify the design content of this article,Perform simulation verification on the overall function of the five-stage pipeline,and the logic instructions,move instructions,arithmetic instructions,memory access instructions and load instructions in the pipeline instructions are simulated and verified,and compare the obtained simulation results with the expected results,which meet the design requirements.Through the synthesis tool DC,based on the SMIC 0.18 μm process library,the logic synthesis of the 32-bit RISC microprocessor of the MIPS instruction set is completed.The target frequency of the synthesis is 50 MHz,and the obtained slack=2.58 ns,which meets the timing requirements of the setup time.The area of the RISC core after DC logic synthesis is 376729.71 μm~2,and the number of gates is approximately 22.4 K gates.The power consumption is 8.40 m W,which meets the design requirements. |
