The Logic Design Of Pipeline Based On 32-bit MIPS Architecture

RISC is the new CPU design technology that developed in 1980s. It's the wholecomputer industry have had a tremendous impact. At present, there are two main linesof RISC and CISC technology, and today the RISC technology is used more and more,which is a characteristic of instructions simple, easy to decode, the use of pipeliningtechnology enables greatly improved its performance. MIPS RISC is a good version, itis very suitable for the use of pipelining.MIPS architecture is introduced in this paper, including a detailed discussion of theregister file, the instruction set, the design of Cache, the structure and performance ofmemory management unit, interrupt/exceptions handling.the effective ways to solvestructual hazard,control hazards and data hazards are offered.the way of increasing thehardware resources is used to solve the structure hazards in the pipeline, the way of dataforwards is used to resolve data hazards in the pipeline,the way of data backforwads andthe way of Branch Target Buffer are used to resolve control hazards in the pipeline,andthe performance of the pipeline is effectively improved by these ways. The numberstages of pipeline is designd for five,the tasks in each stage of the pipeline arereasonably arranged,and the design of each stage in the pipeline is detailedly discussedand showed.the design of the five stages pipeline is used by hardware descriptionlanguage Verilog HDL to achieve, and it is passed in the process of synthesis, functionalsimulation and timing simulation.the results are showed that the function of the designof five stages pipeline is correct,the number instruction executed of every cycle in thepipeline is close approached to one,and the performance of the pipeline is improved.