Jpeg High-speed Encoding Chip Design And Its Performance Is Optimized

In recent years, with the fast development of electronic technology and image compression technology, real-time image processing is widely used in much field. The ICs of image compression/decompression become the core of multimedia techniques, while the research about the algorithm used to ICs is the new key-point in information industry.This article mainly introduced design thought, the structure and the concrete method of the high speed JPEG Baseline Mode Compressed Encoder Chip. And proposed a kind of JPEG image bit-rate control optimized algorithm.At first, the article simply introduced the IC design flow, as well as some related knowledge about JPEG standard. Then it introduced the realization plan in detail, using Top-Down design method. In this design, compression speed was taken as the first considered factor. Therefore, this article proposed a full pipeline VLSI architecture for JPEG image compression standard, optimized the multiplier and the accumulator. At the same time, we have also made the optimization to the area, and proposed area optimization plan. All designs have been download on the Altera Corporation' s Cyclone FPGA chip. The result indicated that designs were entirely accurate, moreover might achieve very high operating frequency.In addition, this paper propose a new BRC(Bit-Rate Control) algorithm using human visual system and rate-distortion approach. The algorithm is absolutely compatible to JPEG exchange format. Experiment result shows that the JPEG file size can be guaranteed to be no more than the given size according to our algorithm, and a better coding effect is acquired.The whole design can be used as the independent JPEG encoder chip, and also could be increased to the other systems as the IP core.