Parallel Architecture Design And FPGA Verification Of Hardware Adaboost Algorithm

Face detection is an important part of computer vision. It is widely used in many fields such as man-machine interaction, video monitoring and etc. However, these fields have more and more requirements of embedded solution. So how to implement real-time face detection on embedded platform is a very valuable research subject. The Cascade face detection scheme based on Adaboost algorithm is better than other algorithms in both detection speed and precision. First, classifier is divided into several stages. Only the windows which can pass all the stages could be judged as human faces. Stages with fewer features are put in front of stages with more features, so the classifier can exclude most of the non-face windows. In this way face detection is speed up without impacting the detection precision. But this algorithm is very complex and needs a lot of memory access, it can not reach real-time face detection with software scheme. With the parallelizability and pipe-line technology of hardware scheme, detection process can be greatly accelerated. This paper presents an array detection architecture based on careful analysis of the Adaboost algorithm and its current hardware implementation. Besides, the solution optimizes the strategy of window scanning and decreases the architecture's memory accessing for external data. Thus the cost of memory bandwidth is greatly cut down.This design is verified on Xilinx Spartan3A1800 DSP FPGA. With video A/D and D/A modules, video stream with VGA resolution (640*480) can be real-time detected with 50MHz system clock.