Design Of Reed-Solomon Encoder And Decoder IP Soft Core Based On VHDL

With the method of IP Core design and on the basis of the encoding-decoding algorithms implementing paths and their relative technologies developed in these fields, a modification of Euclid's algorithm is used to implement the design about the decoding of RS code in this thesis,which adaptively alters its error-correcting capability according to channel state. The latency of the RS encoder and decoder was reduced dramatically through pipeline. A logic operation cell which can be implemented easily is used in the architecture by considering the time and area factor. This architecture achieves an optimization in the area-delay product. simulation verification with QuartusⅡ, the results verify that the design is a complete and feasible one. In this thesis, the parameter of RS code is (255,239), which can correct no more than 8 errors.