| In 2014, the European Telecommunications Standards Institute officially released the Digital Video Broadcasting Satellite-2nd Generation Extension(DVB-S2X) standard, which has higher efficiency of frequency, larger access rate and richer services compared with the Digital Video Broadcasting Satellite-2nd Generation(DVB-S2). Owning to the better performance of the concatenate BCH(Bose Chaudhurl Hocquenghem)+LDPC(Low Density Parity Check) code in DVB-S2, DVB-S2 X still uses this forward error correcting code scheme, but adds more Modulation and Coding modes. DVB-S2 X not only adds 32400 code length, but also adds more new code rates. DVB-S2 X adds 31 kinds of new BCH code rate on the basis of compatible with all 21 kinds of code rate in DVB-S2, which improves flexibility while increases the decoder implementation complexity. Considering the development trend of the multimode chips, this paper designs a configurable BCH encoder and decoder compatible with DVB-T2/C2/S2/S2 X standard. The main contributions of this paper include:Firstly, the thesis introduces the theoretical basis of BCH code and the encoding and decoding principle of BCH code, then emphatically analyzes the BCH decoding algorithm, including the hard decision and the soft decision decoding algorithms. For the hard decision decoding algorithm, BM(Berlekamp Massey) iterative decoding algorithm and its improved algorithms are mainly studied. The Chase decoding algorithm and a kind of soft decision decoding algorithm based on the least reliability position(LRP) are mainly studied for soft decision decoding algorithm. Based on the two kinds of soft decision decoding algorithms, we propose an improved decoding algorithm, which achieves the expected tradeoff between the decoding performance and the implementation complexity. With an error locator evaluator newly added, the improved decoding algorithm can achieve 0.2~0.4d B coding gain compared with hard decision decoding algorithm.Secondly, As far as we know, for the first time we design a configurable BCH encoder and decoder, which is compatible with all BCH code rates in DVB-T2/C2/S2/S2 X standards, and it has the following characteristics:(1) We design a configurable serial BCH encoder, which supports all BCH codes in multiple standards above-mentioned. The synthesis clock of the encoder module can reach 497.07 MHz.(2) The finite field multiplier, which is the basic operation circuit design of BCH decoder, is designed in this thesis. By dividing the general multiplier into two steps, the processing speed is increased. The hardware resources can be decreased through refactoring on different finite field multipliers.(3) The BCH decoder adopts the way of pipeline between three main modules: the syndrome calculator, the key equation solver and the Chien search.(4) For the syndrome calculator and the Chien search, we design the serial and parallel processing respectively. The hardware resource of the optimized 8 bits parallel syndrome calculator is only two times of the serial syndrome calculator.(5) Key equation solver adopts the Si BM iterative algorithm, thus, the multiplier number drops to 1/3 of that of the original realization by reusing the multiplier to calculate three multiplications step by step in the process of each iteration, which reduces the hardware resource.(6) The configurable decoder is compatible with multiple standards, and its synthesis clock can achieve 328.715 MHz.Finally, the hardware FPGA modules of the BCH encoder and decoder are implemented based on VHDL. Simulations and synthesis are performed by using the Modelsim and the ISE software, and the implementation is finally verfied on Xilinx Virtex-7 XC7VX485 T FPGA chip. Results show that the designed BCH decoder can remarkably decreases the error floors of the LDPC codes, i.e., the bit error rate can be less than 1e-10, achieving the expected error correction performance of the concatenated codes. The designed BCH encoder and decoder can also fully support the DVB-S2, DVB-T2, DVB-C2 and DVB-S2 X standards. |
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