Compatible With The Mcs-51 Microcontroller Design

In this thesis, a microcontroller used in SoC is designed. It's based on the present SoC system technology, and completely compatible with the MCS-51 series microcontroller. The traditional MCS-51 is based on CISC architecture, which executes instructions sequentially and translates instructions to microprogram. Because of the reason, the tradition MCS-51 executes instructions slowly. It costs 12 clocks persingle machine cycle instruction. Our design is to speed up MCS-51 and increase its value in SoC system.The microcontroller is based on Harvard architecture, two-stage instruction pipelines and hard-wired logic instead of micro-program. All these technologies speed up the microcontroller's speed and increase its performance. All the modules of the microcontroller are described with Verilog HDL and synthesized with high-level synthesis EDA tools.Do research on parallel design flow, and provide an effective solution that reduce the design cycle and enhance the efficiency at further work.This paper has contributed a lot to the design of the more complex microcontroller. Simulatenously, it has given the way to the design of SoC based on the core of microcontroller.