A Dsp And Cpld-based Image Acquisition And Processing System Research

Recently, with the rapid development of the information technology, all kinds of portable electronic products are coming forth. On the other hand, the collection and processing system makes more and more demands on speed and volume in many consumed electronic products, while the singlechip as a core processor doesn't satisfy the needs of the real time, therefore, it is an urgent affair to search an appropriate processor in the collection and processing system. The Digital Signal Processor (DSP) specially designed for high-speed digital signal processing is playing an important role in the digital field, and DSP with high processing speed and excellent operation performance is particularly adapted to image processing. Owing to the advantages of itself, EDA technology is more and more important in the modern electronic system designs and it has been a basilic embranchment in ASIC technology. Making use of these two technologies, the digital signal processing technology and EDA technology, this thesis researches into an image collection and processing system and then presents a system solution of it.Using DSP (Digital Signal Processor) and CPLD (Complex Programmable Logic Device) as cores of the hardware construction, the system designed in this thesis fulfills the fuction of collecting the digital image from the input analog signals, as well as the fuction of processing the digital image rapidly. It is common to the image collection and processing system which data is less than 1M × 8 bit.The thesis analyzes the characteristics, the working principle and the means of the chip selection, and further more, brings forward a complete set of schemes, on this foundation, fulfills the hardware construction with the DSP and CPLD serving as core processors. This thesis lays emphasis on the hardware circuitry construction and the software design.For the large amount of image data that requires to be processed at one time and the complexity of the processing arithmetic, the inner memory resources of the TMS320VC5402 cann't meet the demand. Aiming at this problem, a scheme of expanding the external memory has been brought forward, which extends theprogram memory, the data memory and the I/O space of DSP separately, with the advantages of flexible interfaces and convenience for operating.According to the specialty of the strong system function and the large program and the request of upgrade convenience, Flash memory is used as a kind of storage medium, when DSP is powered up and reset, the user code is loaded from Flash memory into RAM to run by programming online, this method has the virtues of little cost and flexible programme.In addition, it gives the flow chart of the main program and expatiates on the software implementation methods of the programmable logical function module. The initialization of the system is dissertated here. Finally, some questions and the means settling them in the circuit debuggings are refered to, and some proposals for the advanced optimized system are offered as well.In this scheme, the image collection is dominated by the programmable chip CPLD and the image processing is implemented by DSP, thereby the superiorities of the different types of the programmable chips are exerted, the cost price of the system is reduced, the volume of the product is minished, the performance of the system is enhanced and the expansibility of the system is improved. With the virtues of being small, fast, flexible and easy to carry, this thesis offers some valuable references for image collection and processing system based on DSP and CPLD.