Sub-micron Mos Device Manufacturability Optimization And Design

As the feature size of Integrated Circuit reaching sub-micron, deep sub-micron and even very deep sub-micron, the parameter extraction and optimization in TCAD design are becoming more and more important. What's more, since gap exists between manufacturing value and design value because of the process disturbance, IC virtual manufacturing and design for manufacturability techniques have already become important methods for IC research, process and device physical characteristics analysis.My task is based on the development status quo of IC industry in our country, the technical requirements of TCAD integrative design and optimization, and is instructed by the IC virtual manufacturing and design for manufacturability techniques. And the thesis aims to probe into an optimal approach to process simulation, device physical characteristics simulation and optimization in sub-micron.Firstly, the thesis discusses some small size effects, such as short-channel and narrow-channel effects for threshold voltage, punchthrough effect and hot carrier effect (HCE), etc. Secondly, according to the experimental data, the thesis emphatically and quantitatively studies the influence of substrate doping concentration, substrate bias and channel implant conditions on threshold voltage, and then do the optimization for threshold voltage, after summarizing the structure characteristics of sub-micron MOS devices. The dissertation discusses effective approaches to improve the punchthrough voltage, and also studies the influence of anti-punchthrough ion implant conditions on varies device characteristics. Analyzes the relationships between LDD doping concentration, depth and device characteristics in detail. The device characteristics include channel field, subthreshold slop, etc. Reflects restraint of LDD structure to HCE, while keeping the substrate current as criterion. Finally, with the help of IC virtual manufacturing system—Taurus WorkBench, the process and device simulation are done for a sub-micron MOS device. Using design of experiment, response surface modeling and optimization techniques, the optimal values of selected control factors are got, and the manufacturable designplan is obtained. The ion implant energy and dose adjusting threshold voltage, ion implant energy and dose restraining punchthrough effect and LDD implant dose are chosen as control factors. And the responses of interest are threshold voltage, breakdown voltage of source-substrate or drain-substrate junction and saturated drain current.Based on the studies upward, the optimal non-uniform channel doping conditions are acquired, which are low-energy, high-dose ion implant adjusting threshold voltage, and high-energy, low-dose ion implant restraining punchthrough effect. Three feasible approaches to improve punchthrough voltage are also obtained. They are: 1. Introducing high-energy ion implant restraining punchthrough effect. 2. Adopting LDD structure. 3. Properly increasing the channel length of MOS devices in admitted scope. Finally, the optimal characteristics of LDD structure are got, which are low doping and shallow junction. Further more, because the fluctuation of LDD junction depth is small, the main method to restrain HCE is to adjusting the LDD doping concentration.The thesis goes deep into the process, device physical characteristics, manufacturable design and optimization of sub-micron MOS devices. Prepares for the research of system-on-a-chip (SOC) integrative simulation and optimization in deep sub-micron process.