Research On Chip Manufacturing Yield Optimization And Multi-PVT Point Fast Circuit Simulation Method Considering Process Variation

From the birth of the first semiconductor device to the integration of almost billion transistors on a single chip, the development of integrated circuits (IC) industry has created a technology myth in just a few decades. The rapid development depends on the continuously scaling down of technology size and the innovations in IC design methodology. In the 90’s of last century, the IC design methodology has experienced the revolution from the device-centric generation to the interconnect-centric generation. When the feature size in nowadays IC technology scales down to 45nm, larger and larger process variation causes increasing uncertainty of circuit performance and deteriorates the chip yield. It’s one of the greatest challenges of the traditional integrated circuit design. The IC design methodology is now entering into the third generation of DFM (Design For Manufacturability) and yield-driven, which bridges the gap between design and manufacture.Considering the frequency target, the high-performance circuits (e.g. microprocessors or some high-performance ASIC) are usually designed on the TT (typical-typical) design point. The increasing process variations lead to large spread in chip speed and then reduce the yield, which becomes the critical problem of chip profit. To improve the value of fabricated chips, the concept of speed binning is developed, in which the chips are sorted based on their highest workable frequencies and then sold at different prices. However, the research of binning optimization problem is just taking off, and there is no systematic problem formulation and completed solution up till now. On the other hand, those circuit designs, which are much more sensitive to the parameter variations (e.g. some analog circuits), are in pursuit of great robustness instead of extremely high speed. In addition to the process variations, the variations of the supply voltage and the environmental temperature will also affect the electronic parameters of devices. In order to verify the robustness of a certain design, it is obviously not enough to simulate the circuit only under the nominal condition. It should always be employed the PVT (Process Voltage Temperature) corner analysis during circuit design, which means the same circuit should be repeatedly simulated by SPICE-LIKE simulator with different sets of PVT parameters. However, with the increasing chip size and the enlarged range of PVT conditions, the traditional SPICE-LIKE simulator greatly suffers from the time consumption and therefore is difficult to be applied in multiple PVT corner simulation any more.To optimize the profit of chip manufacturing with speed binning technology, the binning optimization problem for high-performance circuits is systematically formulated, with an objective of the profit function considering the sales revenue, the test cost and the number of bins. Based on the problem, the completed solutions are proposed including the separated solution and the integrated solution, the difference of which is also discussed in the perspective of both theory and experiments. The optimization problem is decomposed into several sub-problems and then solved sequentially. First, to compute the statistical period of a circuit, a sample-based SSTA approach is developed for latched circuits under process variations of arbitrary distribution, where the generalized stochastic collocation method (gSCM) is applied. The statistical problem is translated into a set of deterministic problems on sample points, and therefore the divergency of statistical arrival time is naturally avoided. Second, to maximize the sales revenue, a greedy algorithm is proposed to find the optimal bin boundaries. The unimodality of the reduced objective function is discussed in detail, which guarantees the solution optimality theoretically. Third, to minimize the test cost, an optimal algorithm based on Hu-Tucker coding is proposed to generate the optimal testing order of bin boundaries. The problem of testing order determination is converted to the weighted path length minimization of alphabetic tree. Furthermore, the relationship between the profit and the number of bins is analyzed and then a simple approach is presented to decide the optimal number of bins which leads to the maximum profit.To speed up the circuit simulation of SPICE-LIKE simulator under multiple PVT conditions, the Incremental Analysis Method based on Data-Reuse (DRIAM) is proposed. Adopting DRIAM, the previous obtained simulation results under nominal PVT condition is reused to set up the incremental system systematically in order to enlarge the time step size efficiently. DRIAM has several distinguished advantages as follows. First, applying DRIAM, the Incremental System is always much less singular than the derivative one, therefore the time step size could be enlarged greatly while maintaining the same accuracy. Second, DRIAM is a systematic and easily implemented algorithm. The Incremental System in DRIAM could be constructed directly and automatically. There are no new elements or new state variables added in the Incremental System, and therefore no extra runtime will be introduced. Third, DRIAM can be easily integrated into SPICE-LIKE simulator without any modification of simulation framework. The integration only involves the data reusing, the reconstruction of RHS (right-hand side) matrix and the restoration of output response. Furthermore, DRIAM can be easily embedded into other acceleration methods. Much more speedup can be achieved by applying DRIAM into the single PVT corner simulation of other methods.Some numerical examples are also given in this dissertation to demonstrate all these merits of these proposed algorithms.