High-performance, Low Power Embedded Cpu Integer Unit

With the evolution of IC design methodology IC design shifts for system on chip (SOC) integration. SOC design incorporates a programmable processor, on-chip memory and peripheral function modules. In general, embedded CPU is the core and the most complicated part of SOC. And it is required with low power consumption and low cost. Embedded CPU is used in many diverse applications such as PDA, mobile phone, game machine, etc. It is very depressing that there is not a sophisticated CPU in China. So it is important for us to advance CPU research. As a graduate student of IC design engineering I have been involved in an embedded CPU research project CK510.CK510 is a 32-bit high-performance and low-power embedded CPU. Its instruction set is compatible with M-Core, an advanced RISC microprocessor, which was introduced by Motorola. CK510 employs some new instructions in order to enhance the ability of signal processing. As compared with M-Core, CK510 basically changes the architecture and increases pipeline depth from 4 to 7. In order to gain more performance improvement 8k data cache and 8k instruction cache are used in CK510. Moreover, CK510 employs some low-power design techniques with performance improved. There are three instructions controlling power consumption on system-level and Gated clock technique is widely used in CK510.Integer computing ability is very important for embedded CPU. CK510 only handles integer data and uses Dhrystone, a famous benchmark for measuring integer computing performance, to evaluate its performance.In CK510 project I was in charge of IU (Integer Unit) design. IU consists of three pipeline stages: Register file, Execution and Write Back. It is responsible for decoding, issuing, establishing bypass and transporting instructions to execution unit. IU also deals with some execution units, such as comparator, ALU, shifter, etc. Meanwhile, IU is in charge of retiring instructions and accepting interrupts.In addition to Integer Unit design, I have implemented a front-end automating tool, VPerl, which is a Verilog preprocessor. This tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design and reduce the bug rate significantly.