| With the improvement of the microprocessor's operating frequency and the development of the Instruction Level Parallel technology, the processor can execute more instructions within less time. So, how to provide enough and continuous instruction stream becomes the key to increasing the performance of microprocessors. The Explicitly Parallel Instruction Computing (EPIC) technology combines the advantages of the superscalar and VLIW technologies. Through the communication between the compilers and the hardware, it improves the performance of the processor. Based on the analysis to the traditional Front-end architectures, this paper brings forward a design of instruction fetching component in the Front-End pipeline which increases the efficiency of the instruction fetching by using the multi-level branch prediction structure and the mechanism of the hardware and software cooperating to prefetch instructions.In this paper first we study the basic Front-End pipeline architecture, introduce the EPIC technology and the IA-64 Instruction Set architecture. Then we give the conceptual Front-End pipeline design, it includes the structure of the multi-level branch prediction and the mechanism of the hardware and software cooperating to prefetch instructions which supports the EPIC technology. Secondly, we discuss the characteristic of this prefetch mechanism and its realization in detail. Thirdly, we expatiate on the logic design of the instruction fetching component which supports the instruction prefetch mechanism. We give the designs of the demand fetch and prefetch pipeline, L2 Cache data return pipeline and the mechanism of how to produce a new prefetch request and cancel an old one .We also design and realize the correlative control logics in this component. Finally, the results of the simulation and timing analysis are given which prove that the function of the logics we designed is correct and the delay is within what we desire.
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