Arinc429 Bus Interface Of The Fpga-based Design And Realization

This paper briefly describes the structure of programmable logic devices (CPLD/FPGA), the design flow of Foundation software, the characteristics of hardware description language VHDL and particularly introduces the ARINC429 specifications, the design of ARJNC429 bus interface. The interface design makes full use of the agility and rich resource of FPGA. In the sender, asynchronous FIFO uses the distributed RAM in FPGA. It can save the resource of FPGA and enhance the data rate. In the receiver, the main characteristic of a new method is detecting every bits of ARINC429 signal three times during receiving. This method is more reliable than traditional method. With the result of the designed interface, the xcs10 FPGA experiment board was designed. This experiment board can implement three different configuration modes with xcs10 FPGA, including configuration through the boundary scan pins (JTAG), master serial mode with xc17s10 PROM and slave serial mode with XC9500 CPLD and parallel EPROM. Finally, the test of interface using the enhanced parallel port was done. The test results indicate the designed ARINC429 interface can work properly. This interface of ARINC429 based on FPGA is expedient and reliable. It can avoid the fixed data format and high price of HS-3282.