Design Of Low-Power LVDS Transceiver And High-Speed CML Transmitter

Recently,with the rapid development of communications,networks,and integrated circuits,there have been higher requirements for data transmission volume and transmission speed.However,the traditional interface circuit is limited by technology and can no longer meet the needs of high-speed signal transmission.To solve this problem,Low Voltage Differential Signaling(LVDS)interface technology and Current Mode Logic(CML)interface technology came into being.Based on the SMIC 180 nm CMOS process,this paper designs a low-power LVDS transceiver and a high-speed CML transmitter respectively.In the design of the LVDS transceiver,the transmitter uses a current source drive structure to provide a drive current of 3.5 mA,so as to obtain a differential mode voltage of about 350 mV on a 100 ? matched resistance.In order to obtain a stable driving current,a reference current source circuit is designed using the method of positive and negative temperature coefficient compensation.At the same time,a reference voltage source circuit is also designed to provide a stable common-mode level for the transmitter to ensure the stability of the transmission signal.In addition,because the transmitter is driven by a constant current source,the transmitter still has a current path when it is turned off.Therefore,in order to effectively reduce the power consumption of the chip,a substrate potential control circuit is also designed to dynamically control the substrate of the transistor.Potential to reduce leakage in the off state.In order to broaden the input common-mode level range,a complementary differential rail-to-rail(Rail-to-Rail)receiver circuit is designed,which uses NMOS differential pairs and PMOS differential pairs in parallel to broaden the common-mode level input Range,so that the receiver circuit has a relatively stable output within a larger common-mode input level range.The layout area of the low-power LVDS transceiver designed in this article is 1420 ?m×1150 ?m.The post-simulation results show that the transmission rate can reach 800 Mbps,the power consumption is 120.8 mW,and the output differential mode voltage range is 280 mV?400 mV under 3.3V operating voltage.,which meets the design index requirements.In the design of the CML transmitter,the pre-drive module is used to pre-process the signal.The main drive module adds a 2-tap Finite Impulse Response filter(FIR)to pre-emphasize the signal and reduce Signal loss during high-frequency transmission.Use AC coupling to further process the output signal of the transmitter to make the output comply with the LVDS level standard.The simulation results show that the maximum signal transmission rate of the circuit can reach 2.5 Gbps.