Design Research, Based On A Dedicated Chip Vlsi High-speed Video Decoding

HDTV (High Definition Television) is developed from analogy television to achieve high resolving power of image quality. HDTV video decoder is a key component of high definition television receiver.The design of Video Decoder gets involved with two techniques: video (de)compress theory and VLSI design methodology. The Digital Video Processing technology has been very successfully developed during the passed years. But as to high speed video decoder, there has no perfect realization plan. On the other hand, with the development of the VLSI techniques, the characteristic dimension become smaller and smaller, but the scale become more bigger, megas of gates can integrated into only one small circuit now, it is ready for SOC to exert.Based on the theory of video decompress and VLSI, this dissertation researches on designing, simulation, synthesis and verification of the high speed video decoder for HDTV.There are two kinds of architecture for video processing system: programmable and dedicated. This article analyzes and compares these two architectures, joins the good qualities and withdraws the shortcomings, introduces a mixed structure to instance the video decoder, and then composes two modules (VLD and IDCT) according to their algorithms to show the design method.With the size of the system becomes larger, the difficulty of simulation changes too, so does the proportion of simulation and verification. In common VLSI systems designing, simulation will occupy more than 60 percents of design cycle arid has been the bottleneck of the total process. This paper expands the algorithm and process of simulation, and then put forward new measures to accelerate it using cc simulation method and equivalence checker.When DSM comes into reality, traditional design methodology which contrives logic and physical layer separalely has shown its limitation and deficiency. To solve this problem, a new proactive synthesis strategy is introduced here, it can synchronize logical and physical design world because of accurate wire load model rather than assumption.Summarizing experiences and lessons learned from design course, the author understands that it is inadequate to write only correct codes, it is also needed to write codes that can simulate quickly, synthesis efficiency and has high fault coverage rate. At last, this dissertation advances the coding style and design rules according to fast simulation, nice synthesis and good test generation.