Fpga Bit Stream Generation And Compression

FPGA unique reconfigurable computing technology can not only reduce the development risk and cost of digital system, shorten the time to market, but also effectively lower the maintenance and upgrade costs by dynamic and remote online reconfiguration. Therefore, FPGA is widely used in communication, multimedia, industrial control, numerical computation and etc. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware.In this thesis, we will focus on the architecture research of FPGA. We have particularly investigated all kinds of programmable hardware resources, modeling and describling them and generating the hardware configuration libray file. The bit-generating module extracts the useful information from the mapping module and placement and routing modules, processes and configures the detail hardware resources and generates the bit file. So the user's design netlists go through the mapping step, placement and routing step, bit generating step, generate the configuration file. Then download the bit file to implement the specific design.The dramatic increase in configuration data size has resulted in a corresponding increase in the time required for reconfiguration, it also affects the memory required in configuration. This paper proposes a VLZW compression technique that can get rapid configuration, reduce the memory required for storing FPGA configurations and results in high decompression hardware efficiency. Using this technique, we demonstrate that the compressed bitstream files are 20% the size of the original file on average.