| A Singular Value Decomposition (SVD) hardware architecture is proposed as an alternative to the Brent, Luk, and Van Loan (BLV) systolic array of mesh connected processors. As the matrix dimension (n) increases, resource requirements to calculate the SVD of a matrix using the BLV SVD architecture increases at an exponential rate, limiting SVD usage in embedded real-time systems.;A vector rotation architecture was designed using pipelined CORDIC modules to reduce SVD resource requirements. The memory architecture permits one vector per clock cycle throughput to minimize latency, and a custom controller replaces the BLV systolic array memory interchange requirements. The proposed architecture was implemented in Handel-C, simulated and tested in hardware using a Xilinx FPGA for multiple matrix dimensions and bit widths. The basic SVD was augmented with optional matrix normalization and rank reduction features. Resource requirements and favorable timing measurements demonstrate the feasibility of utilizing RASVD in real-time systems. |
