Research On Design And Implementation Of 65nm Adaptive Bandwidth Phase - Locked Loop

Programmable System Chips are widely used. Its working frequency may spread from tens of megahertz to hundreds of megahertz, which requires that the clock management module of the Programmable System Chips chips must possess great flexibility. Nevertheless, the traditional fixed bandwidth PLL can only achieve the optimal output clock jitter performance in a certain working state. And even, when the reference signal frequency varies slightly larger, the loop might not work properly. However, the adaptive bandwidth PLL can dynamically regulate PLL loop parameters to adapt to different working states, thus realizing the best jitter output clock performance over a wide reference frequency.In this thesis, through research on the principles and structures of the charge pump PLLs, an open loop design method based on loop poles and zeros and phase margins, and a closed loop design method based on natural angular frequency and damping factor are proposed. Based on the research of the principles of the loop, this thesis gives an MATLAB model for the third order PLL and the system simulation, researches on the PLL noise and jitter characteristics, and presents methods to assess the loop noise and jitter. Then the thesis analyzes the necessity of designing Adaptive Bandwidth PLL, deep studies on the principles and implementations of the adaptive bandwidth PLL, entually achieve an adaptive bandwidth phase-locked loop with wide reference frequency range and wide frequency division factor range. Based on previous researches,the influence is pointed out that the feed-forward factor of the switched-capacitor filter gives to the loop, and the thesis amends the parameters of loop bandwidth, dumping factor, etc.According to the functional and performance requirements of the current mainstream Programmable System Chips chips clock management module, based on the adaptive bandwidth PLL technology, this thesis designs the clock management PLL for clock management module. Circuits including VCO and charge pump, etc. are improved, based on previous works, and a new switched-capacitor filter network structure is proposed to suppress more in band noise. The PLL designed in this thesis can work properly with the reference frequency ranging from10MHz to250MHz. The bandwidth can automatically adjust according to reference frequency. The clock multiplication of the PLL can range from2to160, and the frequency of the VCO can range from400MHz to1.6GHz. The PLL provides four-phase clocks. The phase shift function of the PLL can achieve a highest accuracy of62.5ps. The lock time of the PLL is no greater than20us.