Research And Implementation Of Direct - Expansion Receiver Based On Software Radio

Spread spectrum communication because of the secerecy communication, information hiding and strong anti-interference capability advantages, so attracted widespread attention, and it is the key technology of 3G and 4G, is becoming a hotspot. FPGA has fast speed,a rich logic unit, high integration and can be configured flexibly and many other advantages, so it is very popular in the current hardware design. It is very suitable for the realization of wireless communication function based on Software Defined Radio. This paper mainly design a DSSS receiver based on Software Defined Radio theory which used FPGA of Altera company as the hardware carrier.This paper first introduces the basic theory of spread spectrum communication and software defined radio. Secondly, a detailed research in each module of spread spectrum receiver and to determine which algorithm to use, and mainly to solve the problem of the synchronization of DSSS receiver. Then simulate each part of the algorithm in Matlab and proved the correctness of scheme to lay the foundation for the realization of the next step. Finally, using the Verilog hardware description language in the development platform of Quartus II 12.0 to realized the modules of DSSS receiver and given RTL level circuit diagram and block diagram. Carry out functional simulation through Modelsim and realize the expected function, proving its correctness and feasibility.This paper mainly implements the following modules: PN code generating module, digital down conversion module, PN code acquisition module, PN code tracking and carrier synchronization module. The PN code using the code length of 1023 m sequence because of its excellent autocorrelation and cross correlation propertie and easy to replicate, so it is very suitable for use as the spread spectrum code in spread spectrum communication system. Digital down conversion using quadrature frequency conversion. NCO, is the key module of DDC, using the CORDIC algorithm which only consumption logic unit suitable for FPGA implementation. The PN code capture module using the improved FFT algorithm. The improved FFT algorithm which is based on the traditional FFT algorithm carried out 2 times of sampling on the received signal firstly and added a Doppler frequency shift controller, without changing the capture accuracy and anti-interference performance of the shortened the average acquisition time. The PN code tracking module using delay locked loop algorithm which lock two related waveforms of phase difference is almost zero. Carrier synchronization module using Costas loop algorithm which adapt to the idea of software defined radio and carrier synchronization precision.