| Because of the rapid development of communication countermeasure,the security of DSSS system suffers an increasingly threat.The Code Hopping Direct Sequence Spread Spectrum(CH-DSSS)communication makes pseudo-random code hopping over time,which improves the performance of anti-interception and system security.This thesis focuses on the design of a CH-DSSS communication system and the FPGA implementation of the corresponding modules.The main work of the thesis is as follows.1.The overall scheme design of the transmitter and receiver is presented.The Related parameters of the system is given and the selection of FPGA chips is completed.2.The design of a CH pattern that is generated by chaotic sequence in real time is given.And the design of a synchronous head is presented,which has hign gain and can be used for real-time capture.3.The design and FPGA implementation of transmitter baseband scheme is completed,mainly including the modules of data format,code generation,spread spectrum,scrambling,and waveform shaping and so on.The length of spread code is 1024 and code hopping rate is 39.06 k hop/s.The correctness of the design is verified by simulation.4.An improved PMF-FFT algorithm is presented.This method can be used to capture in real time and reduce a lot of logical resource consumption especially for capturing long code.And the design and FPGA implementation of an improved Costas Loop that successively uses different loop parameters is completed.Compared with the single loop parameter,the improved Costas Loop can achieve rapid track of phase and then accurate tracking.5.The design and FPGA implementation of the rest of the receiver baseband scheme is finished,mainly including the modules of matched filter,data distribution,tracking of PN code,de-spread spectrum and so on.And problem of “ inverse ?” on the judgment result is prevented by the detection of bake code.The correctness of the design is also verified by simulation. |
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