Design Of Low Power 16 Bit Resolution Sigma-Delta Modulator

Sigma-Delta ADC is different from Nyquist sample rate ADC. By employing over-sampling principle and noise shaping technique, most noise is removed out of the signal band. Then decimation filter filters out the out-band high frequency shaping noise and achieves higher signal to noise ratio (SNR). The structure reduces sensitivity to analog devices precision and matching. It can realize a resolution which Nyquist sample rate ADC can not reach. This technique has dominated the middle or low speed and high resolution analog to digital data converters.The continuing feature size scaling in CMOS technology has decreased supply voltage to ensure device reliability. Besides, the demand for low-power data converters is increasing for the portable semiconductor requests. Those two requirements impose the low-voltage, low-power data converters popular. Especially for the power management chip of notebook PC battery, a 16 bit low-voltage low-power Sigma-Delta modulator is designed here. It is used for detect the remainder power of the battery.The general situation, basic theory and topology of Sigma-Delta ADC are introduced first. Above this, a third-order feed-forward Sigma-Delta modulator with technology of zeros optimization is designed. Feed-forward architecture reduces swing of internal integrators, which relaxes the op-amp requirement; moreover the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-linearity in op-amp can be suppressed when signal swing is small. It is more appropriate for low-power design. Considering circuit realization, single-bit quantizer makes summing circuit easy to realize. Besides, it has inherent linearity, while multi-bit would decrease the overall linearity and resolution which are limited by the precision of the multi-bit DAC. The technology of zeros optimization enhances the maximum SNR can be achieved, but the difference between capacitors due to the small zero feedback coefficient is huge, which leads to the implementation with capacitors taking up large chip area and more power dissipation. For this, an advanced switched-capacitor(SC) integrator especially for the technology of zeros optimization is used. It can balance the capacitance well.The modulator, designed in SMIC 0.18-μm CMOS process including all analog blocks circuit and layout, achieves a 95dB SNR in a 1 KHz signal bandwidth with 256 KHz clock and 128 OSR, consumes 1.44mW from a 1.8V supply.