85% Based On 0.18¦Ìm Cmos Logic Devices, The Realization Of Miniature Technology

The development of integrated circuits is the progress of integration level. The smaller critical dimension means the better chip performance and lower cost. Since the tool capability and process limit, it's impossible for a Fab to always chase the most advanced process in the world. Digging out the existed tool potential to develop higher integration level process is a good way for a Fab to improve its competitive power and attraction to customer. This paper cooperated with Grace Semiconductor Manufacturing Corporation, and presents the course of 0.18μn shrinking to 0.153μm project. The possibility of 0.18μm process shrink to 0.153μm is verified in this paper and the goal of chip size and cost reduction is successfully achieved. It also provides experience for other shrink project, and successful quest for advanced technology, tool and process limit.GSMC has the capability of mass production from 0.35μm to 0.13μm logic and memory products, and 0.18μm logic CMOS is one of the most important products. If the 0.18μm chip can be shrunk to 85%, the chip area can be reduced about 26% and chip count in one single wafer can be improved about 30% which make the cost turn down significantly.The paper first evaluates the feasibility of the 85% shrink process. The shrunk dimension of every layer is calculated. All layers can meet the capability of GSMC which already mass produce 0.15μm process. Device simulation also showed the device performance and be kept as 0.18μm after shrink and no other obvious side effect. All data proved the probability of the 0.153μm process.Then the original design followed shrink methodology to be taped out, and 0.153μm chip is put into MPW shuttle to verify the process window. For the most critical and important photo process, Focus Energy Matrix is done for ACT, Gate and M1, and data showed the DOF of these layers all meet the mass production requirement. IMP condition and other processes are also revised several round to make the 0.153μm device performance stable and get good Cp yield.The paper also presented the process reliability in the last part, and the chips passed customer product qualification. According to the large amount of inline and WAT data and the new issue happened in the risk run phase, several processes is modified to enhance the process window and reduce the defect. Finally it is implemented that the Cp yield is comparable with 0.18μm.