Research On Yield Prediction Technique For Integrated Circuits

In the past few decades, VLSI manufacturing technology has been advancing according to Moore's Law. The critical dimension of state-of-the-art chip already achieves 22nm, far below the wavelength of the light source used in lithography. The performance and reliability of integrated circuits have been negatively affected by the introduction of new processes and the manufacturing environment, and yield drops. Identification and fix of the root causes of yield losses is becoming a very important topic in semiconductor industry. Design for manufacturability and design for yield are proposed under such a circumstance.We have focused on yield, and the content of this thesis is the yield predicting technique. In semiconductor industry, yield is defined as the ratio of the number of good units of a manufactured product that meets all the requirements in the specification to the total number of manufactured units. Yield is directly related to the profitability on semiconductor products, so it is critical to the business success of integrated circuits projects. Predictability in manufacturing yield is important for production control, material management, timely product delivery and other business factors. Furthermore, by adopting appropriate yield models in yield predicting enables fabricators to analyze the sources of yield losses, thus to establish effective moves to efficiently improve manufacturing yield. Following contents are a summarization of our main research contents and innovations:Implemented a software platform aiming at yield prediction and analysis. Based on the knowledge of yield predicting techniques, we have accomplished the development work of the software, and made special effort to improve its calculation efficiency. The tool passed verification in a mainstream semiconductor foundry in mainland China.Proposed a parallel computing scheme for critical area extraction on state-of-the-art chips. By employing this scheme, the extraction time of critical area is linear with respect to the chip area, the extraction time increases linearly as the chip gets larger. Meanwhile, the space requirement within our scheme is also configurable. These two factors make our tool feasible to handle nano-scale layouts.Improved the accuracy of yield calculation for via layers. In order to increase reliability and reduce the potential for open faults, designers are introducing redundant vias and interconnects. So the single via counting method in via layer yield modeling is not sufficiently precise since it does not take loops into consideration. We come up with an improved method by modeling the problem as a geometric graph problem and an algorithm which extracts loop vias in linear time complexity.Proposed a new layout data structure which outperforms all existing ones taking both time and space into consideration. Layout data structure is the foundation of our yield predicting software and lots of other applications used for post-layout verification. The performance of the layout data structure directly affects the performance of those applications and the user experience. EDA software designers always hope to find better data structures which provide faster access operations and use less memory space at the same time. Compared with HV/VH Tree which is considered as the best choice to date, our new data structure performs region query 30% faster, and uses much less memory.Proposed a yield model for memory chip yield predicting. Due to the existence of redundancies, traditional yield models do not apply to memory chips. We proposed a yield model specially customized for memory layouts. In addition to the regular advantages yield predicting provides, our model enables the designer to optimize redundancy amount and scheme. For instance, designing more redundancies do help increase manufacturing yield, but it also increases the chip size thus decreases the productivity. An accurate yield model helps designer to determine that trade-off. Key words:Design for Manufacturability, Design for Yield, Yield Model, Critical Area, Yield Predicting Technique, Layout Data Structure, Concurrent Programming...