The Study Of Defect Inspection Plans Of Si And Poly Etching For 0.18μm Logic Integrated Circuits

Defect become the main factor affect the yield, based on 0.18μm logic integrated circuit(IC) is more and more stable. In order to keep the competitiveness of the company’s products, setting up more effective defect inspection plans are very necessary. In the manufacture of integrated circuits, Si and Poly etching are important processes to realize the shallow trench isolation(STI) and define gate of transistor. Si residue and Poly residue which are the key defects at defect inspection after etching(AEI), will directly lead to device fail. So, it’s very necessary to study the defect inspection plan of Si and Poly AEI.Currently, there are two problems in defect inspection of Si and Poly after etching. One is when baseline yield trend down happened, yield loss wasn’t matching with key defect baseline which is in order to prevent baseline yield trend down. It is found the reason by analysis is bright field scan results contained more nuisances, which led to key defect baseline values is not accurate. In this paper, fine-tuning KLA scan recipe to separate the nuisance and ensure the baseline value accurate, by adjusting scan recipe parameter; applying automatic defect classification filtering; changing edge contrast mode. Do feasibility analyzing and reliability test for above three methods by experiment, which shows automatic defect classification filtering is applicable to setup scan recipe for Si AEI and edge contrast mode is applicable to setup scan recipe for Poly AEI. Finally, the yield loss is matching with key defect baseline after applying the improved KLA scan recipe to production, and preventing the baseline yield trend down effectively.Another problem is in-line found some lots’ yield is lower than average yield. It is found the reasons by analysis were production capacity fast growing, but defect scan tools didn’t increased when process tools increased, which led to KLA inspection capacity was insufficient. Another reason was the existing simple and random sampling system appeared missing sampling because of process tools increased. And the two reasons caused impacted lot count trend up when process excursion happened, and increased the risk of some lots low yield. In this paper, choosing dark filed scan tools to do Si and Poly after etching inspection to expand defect inspection capacity. Analyzing the residue defect capture rate of AIT and Compass by experiment, the results show Compass’ s capture rates are 64.8% for Si residue, 63.5% for Poly residue, which are higher than AIT and more suitable to Si and Poly after etching inspection. After applying it to production by update the defect inspection flow, the capacities of Si and Poly etching defect inspection improve 74%. For improve sampling plans, in this pare based on characteristics analyzing of IC manufacture and etching process tools, setting up the sampling plan which is firstly stratified sampling by etching process tools and then systematic sampling in sample group, combining by run lot count sampling, by runtime sampling and by equipment status changing sampling. The sampling plan is stable, uniformly and timely by one month keep tracing. Finally, the impacted lot count trend down 55%, and the risk of some lots low yield reduce effectively, after above two improve plans applied to production.