0.13?m CMOS Logic Device 90% Shrink And Al Electric Migrate Reliability Improve

The integrated circuit has been developed more than half century. The integration level improved continually. Integrated circuit has become to super-large-scale integration from large-scale integration in 21 century. The number of transistor in one chip increase constantly, when critical dimension has become smaller. Chip performance will be better when size down, and cost of one chip also be reduced. Because of tool performance and process margin not enough, it's difficult for a fabrication to always keep the most advanced process, work out advanced chip in the world. Developing out the already existed tool, to find higher integration process is a fine way for a fabrication to improve competitiveness and provide more profit customer. In HHGrace Semiconductor Manufacturing Corporation(HHGrace), has 0.13?m platform. We base on 0.13?m platform do 90% shrink. It provides experience for other shrink project. In this project, we verified shrink method feasibility and critical layer litho process window. For electronic migration fail reliability issue, we through change some process recipes make 0.117?m platform electronic migration can pass reliability test.HHGrace has process experience on logic and flash CMOS device, the fabrication process CD cover 0.25?m to 0.13?m of mass production, and 0.13?m logic CMOS platform is one of the smallest CD platform. If shrink is successful, single chip size will be 0.8 multiple smaller than 0.13?m at the best condition. Chip number will 1.23 multiple more than 0.13?m. and customer cost will drop to 0.8 multiple.This paper, at first we analyze single device 90% shrink way. And discuss about layout create. Also we need verified litho process window. Because 0.13?m is smallest process size in HHGrace, so this shrink project has no other example. Some critical layers process window check is necessary. Follow formulate shrink rule, change 0.13?m layout from customer design. Use MPW wafer do some verify experiment. We do litho process window verify for critical layer. According to focus and energy matrix experiment data for Act, Gate and first metal layer. We can see the DOF of these layers has 0.3~0.4?m litho window. To make device can keep performance after shrink. We need tune IMP recipe, because of device size change.At last, point at Electronic migration fail rate high find at 0.117?m platform, we study improve ways. Electronic migration(EM) will be worse, when Al CD has been sized down after shrink. According to available phenomenon, change some process recipe. After these change, Al Electronic migration can pass reliability test.